1. Field of the Invention
This invention relates in general to semiconductor devices and more specifically to annealing an epitaxial layer in a semiconductor device.
2. Description of the Related Art
Semiconductor devices utilize epitaxially grown material that includes carbon or tin. Examples of such materials include alloys containing two or more of silicon, germanium, carbon, and tin. The addition of tin or carbon to a silicon or germanium layer may present difficulties due to relatively large lattice mismatches and phase diagram differences. For example, a silicon lattice has a spacing of 5.43 Angstroms and a germanium lattice has a spacing of 5.65 Angstroms. Tin has a lattice spacing of 6.49 Angstroms and diamond carbon has a lattice spacing of 3.57 Angstroms.
The lattice constant of relaxed carbon-doped silicon is smaller than that of silicon. Accordingly, a carbon-doped silicon layer epitaxially grown on a silicon layer may be under stress due to lattice constant mismatch. Such a strained layer may be used in semiconductor devices for enhanced performance.
One problem with epitaxial silicon carbon (or other layers having carbon) is that the material is thermally unstable. Thermal annealing at temperatures greater than 900 C may cause the conversion of carbon from substitutional to interstitial lattice sites, thereby increasing the lattice constant. Accordingly, by annealing the layer at a high temperature, the strain of an epitaxially grown silicon carbon alloy layer may undesirably decrease.
What is needed is an improved technique for annealing a carbon or tin alloy material.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.